The level of integration in semiconductor integrated circuits continues to increase. The next generation of dynamic memories will have a capacity of 64 megabits and that of microprocessors will have upwards of ten million transistors. Further generations are being planned. These densities are obtainable only by the continuing shrinkage of feature sizes, now pushing towards 0.15 .mu.m. However, layer thicknesses cannot similarly shrink because of physical effects such as dielectric breakdown and resistive losses. Hence, current designs call for features with high aspect ratios, that is, the ratio of the depth of a feature to its width. For example, a via electrically connects two levels of metallization through an intervening dielectric layer. Since the dielectric layer is constrained to a moderately large thickness because of dielectric breakdown thresholds, a dense circuit requires very narrow vias, and the resulting aspect ratios are three and higher. Etching high aspect ratio holes requires a highly anisotropic etch.
A further problem is that for economic reasons, the size of wafers being processed is increasing. Most current high-production equipment is designed for 200 mm wafers, and equipment is being designed for 300 mm wafers. Such large wafers impose stringent uniformity requirements on the etching process.
Some of the increased density is being achieved by using more complex integrated circuit structures, which however impose additional requirements upon the processing, particularly in etching. An example is the structure for a bi-level contact shown cross section in FIG. 1. A silicon substrate 10 includes unillustrated structure already formed therein that requires contacting from an upper level. A first oxide layer 12, for example, of plasma-deposited silicon dioxide, is formed over the silicon substrate 10. A relatively thin polysilicon interconnect 14 is deposited and defined over the first oxide layer 12, and a second oxide layer 16 is deposited over both the interconnect 14 and the first oxide layer 10. Thereafter, a single photolithographic etching step using a single photomask etches both a relatively shallow via hole 20 to the polysilicon interconnect 14 and a deeper substrate contact hole 22 to the silicon substrate 10. It is to be appreciated that a very similar process may be used where both of the holes are used to contact respective polysilicon interconnects on different levels.
The bi-level contact structure requires an etch process that is highly selective to silicon. That is, a process that selectively etches silicon oxide but etches silicon to a much less extent. If the selectivity is insufficiently high, the polysilicon interconnect 14 would be etched through while, under the same etching conditions, the thicker first oxide layer 12 is being etched through. Even in a less demanding structure, selectivity to silicon is greatly desired so that the oxide etch dependably stops on the underlying silicon to thus provide a wide process window for the etching. With poor selectivity, if the etch were performed for too short a time, the silicon would not be exposed, and if it were performed for too long a time relatively thin underlying silicon layers would be etched through. Process variables make a precisely timed etch difficult to implement commercially.
Oxide etch selectivity has been achieved in a plasma reactor with a fluorocarbon etching gas and a fluorine scavenger. A fluorocarbon as used in this application is a compound consisting only of carbon, fluorine, and possibly hydrogen. A hydrogen-free fluorocarbon consists only of carbon and fluorine. Examples of hydrogen-free fluorocarbon etching gases are CF.sub.4, C.sub.2 F.sub.6, C.sub.4 F.sub.8. On the other hand, a hydrofluorocarbon compound also contains at least one carbon atom, for example, CHF.sub.3. It is believed that under common conditions most fluorocarbon gases deposit a polymer on all surfaces. However, if the polymer has a sufficiently low fluorine content, oxygen in an underlying silica (SiO.sub.2) layer reacts with the polymer to form volatile CO and CO.sub.2. That is, the underlying silica prevents the polymer from being formed, and the silica is etched. On the other hand, an underlying layer of silicon (or silicon nitride, Si.sub.3 N.sub.4) does not contain oxygen, and the polymer deposits faster than it is etched to thereby protect the underlying silicon layer from being etched. As a result, etching of the via and contact holes 20, 22 proceeds until silicon layers 14, 10 are reached, at which point etching stops or is substantially reduced.
The selectivity provided by the polymer depends, however, on the polymer having a relatively low fluorine content. Silicon is the most preferable of a number of materials known to scavenge fluorine from a fluorocarbon plasma. The silicon reacts with the fluorine radicals F* in the plasma, and any polymer resulting from the plasma then has a low fluorine content. Generally, however, the silicon requires some activation. Rice discloses thermal activation of the silicon in U.S. Pat. No. 5,477,975. It has been recognized that alternatively the silicon can be activated with RF biasing of the silicon electrode. See for example U.S. Pat. No. 5,556,501 to Collins et al. and European Patent Application 552,491-A1.
Schneider et al. in U.S. patent application Ser. No. 08/734,015, filed Oct. 18, 1996, incorporated herein by reference, address these many problems involved in oxide etching. Among several embodiments, they disclose the conically shaped plasma reactor 30 illustrated in cross section in FIG. 2. A wafer 32 is supported on a pedestal 34 that is preferably vertically movable with respect to a lower chamber body 36. A ring 37 surrounds the upper portion of the pedestal 34. In the examples described here, the ring 37 is composed of quartz and is left thermally floating. However, it is possible to form the ring 37 of silicon or silicon carbide and use it as a thermally activated fluorine scavenger. The heating can either rely upon the balance between plasma heating and active cooling or can rely upon, for example, controlled radiant heating of the silicon ring 37 if higher activation of the ring is desired.
An upper chamber assembly includes a conical dome 38 supported on the lower chamber body 36 through an electrical insulating joint including a plasma guard 40, a seal ring 42, and intervening support pads 44. Preferably, the conical dome is composed of an electrically insulating bulk body of sintered silicon carbide and an electrically conductive inner film of chemical vapor deposited (CVD) silicon carbide. Alternatively, the conical dome can be composed of high resistivity (.rho.&gt;20 .OMEGA.-cm) polysilicon material. An RF inductive coil 46 supported in a coil carrier 48 is wrapped around the conical dome 38. The resistivities of the sintered and CVD silicon carbide portions of the conical dome 38 are chosen such that the RF magnetic field induced through the inductive coil 46 can pass through the dome 38 with minimal loss but the inner CVD film can be set to a predetermined electrical potential to provide a grounding plane.
An electrically insulating plasma guard 50 rests on the top inner rim of the conical dome 38 and in turn supports a roof 52. A vacuum O-ring or Vespel ring provides the electrical isolation. A center gas feed 54 is integrated with the roof 52 and supplies processing gas into the reactor 30 through unillustrated holes in the roof 52. Most of the remaining illustrated structure is involved with the temperature control of the conical dome 38 and the roof 52 and is fully described in the referenced patent application to Schneider et al. The roof thermal control includes a resistively heated plate 56 and a water-cooled chiller plate 57. The dome thermal control includes a resistively heated conical sheath 58 and a water-cooled collar 59.
The diameter of the exposed portions of the roof 52 is approximately equal to the diameter of the pedestal. That is, the two electrodes sandwiching the plasma have the same size.
For an oxide etcher, the roof 52 is preferably formed of an electrically conductive fluorine scavenger, examples of which are polysilicon, silicon carbide, and glassy carbon. Preferably, the conical dome 38 is formed of one of these same materials and has a conductivity sufficient to present an electrical grounding surface to the plasma. Typically, the etching gas is a fluorocarbon, and hexafluoro-ethane (C.sub.2 F.sub.6) has been extensively tested in the illustrated reactor for oxide etching. When RF power, typically in the frequency range of 1 to 2 MHz, is applied both to the coil 46 and across the two electrodes formed by the pedestal 34 and the roof 52, a fluorocarbon plasma is excited in the reactor 30, including a processing space 56 above the wafer 32. The fluorine scavenger is made to contact the plasma and to remove a certain amount of fluorine from the plasma. Thereby, any polymer formed on the wafer 32 from the fluorocarbon plasma is deficient in fluorine. As is now well known, a low-fluorine polymer can produce a highly selective etch to silicon, for example, in the bi-level contact structure of FIG. 1. In this approach, the activation is accomplished with substantially no heating of the roof and dome.
It is now known that one way to activate the solid fluorine scavenger is to apply RF energy to it. That is, the roof 52 is not merely grounded, but a significant RF signal is applied to it. As is shown in U.S. patent application Ser. No. 08/804,430, filed Feb. 21, 1997 by Wu et al., the electrical circuit in this use is illustrated schematically in FIG. 4. The conical dome 38 is electrically grounded, and its surrounding coil 46 is powered by a first RF power supply 60. A power-splitting RF power supply 62 is coupled through two coupling capacitors 64, 66 to both the roof 52 and the pedestal 34. An example of a power-splitting RF power supply 62 is schematically illustrated in FIG. 4. A second RF power supply 66 supplies single-phase RF power to a power splitting circuit 68. For example, the RF power is applied to the primary of a wide-band transformer 70. The secondary of the transformer 72 has a number of taps, and a switch 72 selectively connects any one of these taps to a predetermined potential such as ground. Respective ends of the transformer secondary are connected through the coupling capacitors 64, 66 to the roof 52 and the pedestal 34. Dependent upon the setting of the transformer tap switch 72, varying amounts of RF power are split between the roof 52 and the pedestal 34. In the illustrated position at the midpoint of the transformer secondary (which is not a recommended position, a lower fraction of RF power delivered to the roof 52 being desired) and assuming equal sizes for the roof 52 and the pedestal 34, equal amounts of RF power are delivered to the roof 52 and the pedestal. On the other hand, if a tap at the roof end of the transformer secondary is switched to ground, then the roof 52 is AC grounded and no RF power is delivered to the roof 52. This is the mode of operation that has been used by Rice et al. when the silicon-based fluorine scavenger is thermally activated. Tap positions between these two extremes split different ratios of power with a majority of power going to the pedestal 34.
Silicon-based scavenging for fluorine in the presence of a fluorocarbon etchant has also been applied to achieve high selectivity of oxide etching to an underlying layer of silicon nitride. Marks et al. disclose in U.S. Pat. No. 5,423,945 high selectivity to nitride can be achieved by use of either a silicon counter electrode or using a silicon-containing gas such as silane, but they offer the solid and gaseous silicon sources as alternatives.
Collins et al. have described an alternative approach to fluorine scavenging in U.S. Pat. No. 5,556,501. In one of several embodiments, they combine a fluorocarbon etching gas, such as C.sub.2 F.sub.6 or CF.sub.4, with a fluorine-consuming silicon-containing additive gas, such as silane (SiH.sub.4), tetraethylorthosilicate (TEOS), diethylsilane, or silicon tetrafluoride (SiF.sub.4). They also recommend using a polymer-forming additive gas such as CH.sub.3 F or CHF.sub.3. The same patent and its second-generation continuation application Ser. No. 07/941,507, filed Sep. 9, 1992, published as European Patent Application 552,491-A1, also disclose a silicon counter electrode and even RF powering of that electrode. However, Collins et al. consider the solid silicon scavenger as an alternative to a gaseous fluorine scavenger. Similarly, Tatsumi in U.S. Pat. No. 5,312,518 discloses both a silicon wall for scavenging fluorine in a sulfur halide etch and also discusses a C.sub.4 F.sub.8 etch, but he does not combine the two chemistries.
The power splitting discussed by Wu et al. provides good oxide selectivity at relatively lower temperatures, but it is desired to reduce the temperature even further, particularly to simplify the reactor design and lengthen the lifetime of temperature-sensitive parts such as O-rings. Also, RF activation of the solid silicon-based scavenger requires that an RF signal be applied to the roof, a further complication in the design and operation of the reactor.